Arteris, Inc. announced on June 17, 2025, an expansion of its multi-die solution, delivering foundational technology for rapid chiplet-based innovation. This addresses the industry's shift towards multi-die systems as computational power demands, especially from AI workloads, increasingly exceed what traditional monolithic die designs can provide.
The expanded solution aims to reduce chiplet and SoC design time and optimize power, performance, and area bottlenecks by providing key Network-on-Chip (NoC) IP technology for standardized die-to-die communication. It also automates key SoC creation workflows, built for interoperability with standards like Universal Chiplet Interconnect Express (UCIe), Arm AMBA protocols, and PCIe.
Arteris is collaborating with leading players across the silicon value chain, including Cadence, Synopsys, and global fabs, to ensure a ready-to-deploy solution. This strategic momentum positions Arteris as a critical enabler for next-generation AI and automotive platforms, allowing semiconductor firms to compress development cycles and deliver differentiated AI performance.
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