Arteris, Inc. announced an innovative evolution of its network-on-chip (NoC) IP products on October 15, 2024, introducing tiling capabilities and extended mesh topology support. This new functionality is designed to accelerate the development of Artificial Intelligence (AI) and Machine Learning (ML) compute in system-on-chip (SoC) designs.
The new approach enables design teams to scale compute performance by more than 10 times while adhering to project schedules and power, performance, and area (PPA) goals. It also facilitates the creation of modular, scalable designs by replicating soft tiles across the chip, which condenses design time, speeds testing, and reduces design risk.
This combination of tiling and mesh topologies within Arteris’ flagship FlexNoC and Ncore IP products can reduce auxiliary processing unit (XPU) sub-system design time and overall SoC connectivity execution time by up to 50% compared to manually integrated designs. The expanded AI support is now available to early-access customers and partners, addressing sophisticated AI workloads for vision, machine learning models, deep learning, natural language processing, and generative AI.
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