Cadence announced a new Chiplet Spec‑to‑Packaged Parts ecosystem that brings together pre‑validated partner IP, a physical AI chiplet platform, and advanced interconnect to streamline design and reduce time‑to‑market for AI, data‑center, and high‑performance computing customers.
The ecosystem incorporates IP from Arm, Samsung Foundry, and other silicon vendors, allowing designers to assemble and prototype chiplets using Cadence’s Physical AI chiplet platform and Xcelium logic simulator. A silicon prototype built on Samsung’s SF5A process demonstrates the platform’s readiness for advanced nodes and validates the UCIe (Universal Chiplet Interconnect Express) interconnect standard.
By integrating validated IP and real‑time design‑flow feedback, the solution lowers engineering complexity and shortens development cycles. Cadence positions the ecosystem as a bridge between traditional EDA tools and system‑level design, including digital twins, giving customers a comprehensive path from specification to packaged parts.
The launch aligns with the semiconductor industry’s shift toward chiplet architectures, driven by the need for higher yield, flexibility, and AI‑specific performance. Cadence’s focus on UCIe and its partnership with leading IP providers places it in a strong competitive position against rivals such as Synopsys, while its recent financial results and robust backlog signal continued demand for its tools.
CEO Anirudh Devgan emphasized that the ecosystem “expands Cadence’s ability to serve the growing AI market by enabling modular, high‑performance chiplets that can be rapidly integrated into customer designs.” CFO John Wall highlighted the company’s record backlog and guidance for continued revenue growth, underscoring confidence in the chiplet strategy.
The ecosystem is expected to accelerate the adoption of chiplet solutions across data‑center, automotive, robotics, and cloud‑edge markets, positioning Cadence as a key enabler of the next generation of AI‑accelerated silicon.
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